Mission Critical Design – Training Course

As such designing these solutions requires the designer to not only understand what techniques can be used at the logic level but also, the wider systematic, regulatory and environmental issues.
This course will therefore present the environmental challenges and what they mean to the logic designer. Along with introducing high level concepts such as SIL level, Reliability and Mean Time to Failure, attendees will also gain an understanding of the importance of engineering governance.

The focus of this course is the development of techniques which can be used in programmable logic including Clocking & Reset strategy, Triple Modular Redundancy, IO Planning, Safe State Machines and Counters, Error Correcting Codes, Single Event Effect Mitigation along with Verification strategies and metrics, formal equivalence checking, Synthesis strategies and several other advanced techniques.
Each session will complete with a Lab which will demonstrate the concepts outlined in the session. Attendees will at the completion of the course have a detailed understanding of the challenges and strategies to address the creation of mission critical systems for a wide range of applications.

Agenda
• How the environment impacts our designs
• Temperature, Shock & Vibration, EMC and Radiation
• Programmatic / System level considerations.
• Different Standards 61508 / DO254 / ISO 26262
• The design life cycles
• Engineering Governance
• What is reliability & What does MTBF Mean & What impacts the MTBF
• Requirement capture & Progressive Verification
• Architectural design & Inter dependency of faults between SW and HW
• Common Cause Failures & Failure Mode & Redundancy
• Worse Case Analysis
• FPGA Design Considerations
• FPGA Development overview & Supporting Documentation
• Device Selection – OTP, FLASH, SRAM –
• Coding Style & Certified tools including
• D0254 and IEC61508 applicable standards
• Failure modes
• Different Types – Stuck At, Babbling, Data / Configuration Corruption
• Consideration during the FPGA deign process.
• Self-Test and Diagnostics
• Clocks and Rest & IO Planning & JTAG / Boundary Scan
• Safer State Machines & Counters
• Considerations for failure modes
• Design Techniques
• Synthesis Considerations
• Error Correcting Codes Communications and Memories
• Design Considerations for BRAM ECC
• Triple Modular Redundancy Local, Fine Gain and Global
• Different types of TMR and associated trade-off
• Functional Separation within the device,
• What are the objectives of isolation?
• What flow are available.
• Xilinx Isolation flow
• Single Event Effects and Configuration Corruption
• What are they within in our design – Where do they occur
• Addressing Configuration SRAM issues
• Verification & Verification Metrics & Frameworks
• Synthesis Tools
• Working with different synthesis tools for high reliability
• Include synplify and precision
• Fault Injection
• Timing Closure
• Advanced Features e.g. XADC, SysMon

Labs Include
• Part Stress Analysis – FPGA and Board Example
• FMECA Lab Analysis – FPGA and Board Example
• State Machine – Design and Synthesis Lab
• FPGA Coding and Code Review Lab
• MicroSemi Libero High Reliability State Machine Design
• MicroSemi Libero BRAM EDAC
• Xilinx Isolation Flow – How to segment design in logic and verify
• Xilinx TMR MicroBlaze – How to create a TMR MicroBlaze solution
• Code coverage Lab – Mentor Graphics ModelSim Required

Applicable Technologies: – These techniques outlined in this course can be applied to any FPGA technology. For reference course Xilinx Seven Series and Microsemi ProAsic 3 devices will be targeted.